Conventional methods of fabricating back-end-of-line (BEOL) metal interconnect layers employ a copper or copper alloy (Cu) inlay or damascene process, because of difficulties in patterning blanket Cu metal films into interconnect traces. As reductions in device scaling continue, front-end-of-line (FEOL) transistor size becomes smaller, and the number of transistors per unit area increases. Correspondingly, BEOL metal interconnect line pitch decreases. As the metal trench width is reduced, the trench aspect ratio increases, making it increasingly more difficult to deposit barrier/seed layers with good uniformity and integrity, and without creating voids, which cause reliability and yield problems and high line resistance. Grain growth in small features is also limited, which degrades electromigration (EM). In addition, with the dual damascene approach the low-k dielectric in which the trenches are etched becomes damaged by the etch processes, thereby degrading capacitance and time-dependent dielectric breakdown (TDDB).
Reactive ion etching (RIE) or short RIE has also been used for aluminum (Al), as it has the advantage of producing an anisotropic or directional etch pattern. This allows for approximately rectangular interconnect cross sections, which in turn allows for high interconnect densities, as required for modern microchips. However, RIE is difficult to apply to Cu, because Cu does not readily form volatile compounds for a dry etching process, except with high temperatures that are destructive to the semiconductor features. Furthermore, chloride used for dry etching poisons Cu.
Conventional subtractive Al RIE processes also involve a large number of steps. Specifically, blanket Al is patterned to form metal lines, a dielectric layer is formed, vias are etched in the dielectric, and the vias are filled with tungsten (W). In addition, similar to the dual damascene process, the dielectric becomes damaged during the etching of the vias, thereby diminishing the benefits of using a low-k dielectric. Further, W vias have a higher electrical resistance than Al.
A need therefore exists for improved methodology with fewer steps enabling the formation of metal interconnects and vias with improved uniformity and electromigration, without degrading the low-k dielectric, particularly for 100 nm pitch devices and smaller.